Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are fabricated on or in a surface of a wafer, or alternatively, on a surface of a previous layer. This fabrication process typically requires subsequent layers to be fabricated upon a smooth, planar surface of a previous layer. However, the surface topography of layers may be uneven due to an uneven topography associated with an underlying layer. As a result, a layer may need to be polished in order to present a smooth, planar surface for a subsequent processing step. For example, a layer may need to be polished prior to formation of a conductor layer or pattern on an outer surface of the layer.
In general, a semiconductor wafer may be polished to remove high topography and surface defects such as scratches, roughness, or embedded particles of dirt or dust. The polishing process typically is accomplished with a polishing system that includes top and bottom platens (e.g. a polishing table and a wafer carrier or holder), between which the semiconductor wafer is positioned. The platens are moved relative to each other thereby causing material to be removed from the surface of the wafer. This polishing process is often referred to as mechanical planarization (MP) and is utilized to improve the quality and reliability of semiconductor devices. The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates, along with the selective removal of materials fabricated on the semiconductor wafer. This polishing process is often referred to as chemical mechanical planarization or chemical mechanical polishing (CMP).
In these polishing processes, it is often important to determine when an outer layer or film has been polished to a desired planarity level. In particular, it is desirable to know when the outer layer of the semiconductor wafer has been polished to a planarity level which is acceptable for presentation of the wafer to a subsequent fabrication process.
In order to determine when a wafer has been polished to a desired planarity level, systems and techniques have heretofore been utilized which polish the wafer down to a predetermined thickness. For example, a typical method employed for determining when the wafer has been polished down to a predetermined thickness is to measure the amount of time needed to planarize a first wafer to the desired thickness, and thereafter polishing the remaining wafers for a similar amount of time. In practice this method is extremely time consuming since machine operators must inspect each wafer (e.g. measure the thickness thereof) after polishing. In particular, it is extremely difficult to precisely control the removal rate of material since the removal rate may vary during the polishing of an individual wafer. Moreover, the removal rate may be diminished in the process of polishing a number of wafers in sequence. Yet further, such methods do not actually measure the planarity of the outer layer, but rather simply make an assumption that the outer layer has been polished to an acceptable planarity level when the wafer is polished to the desired thickness.
Another method employed for determining if the wafer has reached the desired thickness is to impinge a light beam, such as a laser light beam, onto the semiconductor wafer in order to determine the thickness of the wafer. Various techniques have been used to detect when an outer film associated with the semiconductor wafer reaches the desired thickness. For example, the apparatus disclosed in U.S. Pat. No. 5,151,584 issued to Ebbing et al directs an incident laser beam onto the surface of a semi-transparent thin film (e.g. silicon dioxide) of a semiconductor wafer during etching thereof. A first portion of the incident beam is reflected from the top surface of the film, and a second portion of the incident beam is reflected from the bottom surface of the film. Since the film has a finite thickness, the two reflections will either constructively or destructively interfere with one another. As the layer is etched, its thickness is changed thereby cycling intensity of the reflected beam through constructive and destructive interference patterns which may be utilized to determine when the wafer has been etched to the desired thickness. Such a technique has a number of drawbacks associated therewith. For example, such a technique may only be utilized after certain steps in the fabrication process. For example, such a technique may be useful for measuring thickness of a blank wafer, but has been found to perform unsatisfactorily when utilized to measure thickness of a patterned wafer. Moreover, similarly to the manual inspection method discussed above, such a technique does not actually measure the planarity of the outer layer, but rather simply makes an assumption that the outer layer has been polished to an acceptable planarity level when the wafer is etched down to the desired thickness.
In order to overcome the above-mentioned drawbacks associated with wafer thickness-based polishing endpoint techniques, a number of techniques have heretofore been utilized in an attempt to measure the actual planarity of the outer layer of the wafer. For example, a method which has heretofore been employed for determining when the wafer has been polished to a desired planarity level is to periodically remove the wafer from the polishing system, and thereafter measure the planarity of the wafer with an instrument such as an atomic force microscope or a profilometer. If the wafer has been polished to the desired planarity level, the wafer is released to a subsequent fabrication step. However, if the wafer has not been polished to the desired planarity level, the wafer must be placed back into the polishing system for further polishing thereof. It should be appreciated that numerous measurements may be required to reach the desired planarity level. Hence, in practice this method is extremely time consuming since machine operators must measure each wafer (i.e. measure the planarity thereof) a number of times during the polishing process.
Thus, a continuing need exists for a method and an apparatus for in situ measurement of the planarity of the outer layer of a semiconductor wafer during polishing thereof.